As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design have resulted in the development of three dimensional designs, such as fin field effect transistors (FinFETs). A typical FinFET is fabricated with a fin extending from a substrate, for example, by etching into silicon of the substrate. The channel of the FinFET is formed in the vertical fin. A gate structure is provided over (e.g., overlying to wrap) the fin. It is beneficial to have a gate structure on the channel allowing gate control of the channel at the gate structure. FinFET devices provide numerous advantages, including reduced short channel effects and increased current flow.
As device dimensions continue scaling down, FinFET device performance can be improved by using a metal gate electrode instead of a typical polysilicon gate electrode. One process of forming a metal gate stack is implementing a replacement gate process (also called as a “gate-last” process) in which the final gate stack is fabricated “last”. In some gate processes, voltage threshold tuning is achieved by deposition of metal films with different work functions correlated to the intrinsic properties and thicknesses of the metal films. As device dimensions shrink, threshold voltage (Vt) tuning with these techniques can become more difficult.